feat: MiniMax M2.5 PD Disaggregation Recipe (1P2D, MoRI-EP + MoRI-IO)#999

Draft

ChuanLi1101 wants to merge 22 commits intoSemiAnalysisAI:mainfrom

ChuanLi1101:chuali/minimax-m25-vllm-disagg

Commits on Mar 11, 2026

[AMD] Add vLLM disaggregated prefill-decode benchmark for MI355X
chunfangamd
committed
[AMD] Refactor vLLM disagg recipe: models.yaml, UCX cleanup, QoS support
chunfangamd
committed
[AMD] Update vLLM disagg recipe for v0.17.1 NixlConnector API
chunfangamd
committed

Commits on Mar 12, 2026

[AMD] Make vLLM disagg recipe CI-compatible (mia1 cluster)
chunfangamd
committed
[AMD] Co-locate vLLM disagg router with prefill on NODE_RANK=0
chunfangamd
committed
[AMD] Use public vLLM base image with runtime dependency install
chunfangamd
committed

Commits on Mar 13, 2026

Commits on Mar 17, 2026

Commits on Mar 19, 2026

[AMD] Fix vLLM disagg hang: READ mode support + safety timeouts
chunfangamd
committed

Commits on Mar 21, 2026

Adapt vLLM disagg recipe for 9N mia1 cluster (mlx5 NICs)
chunfangamd
committed

Commits on Mar 23, 2026

Commits on Mar 24, 2026

[AMD] Enable reading PREFILL_TP,PREFILL_EP,PREFILL_DP_ATTN,DECODE_TP,DECODE_EP,DECODE_DP_ATTN from amd-master.yaml config.
ichbinblau
committed

Commits on Mar 25, 2026

Merge branch 'main' into chun-oren-theresa/vllm_disagg
chunfangamd
committed

Commits on Apr 2, 2026