Shanthi Priya:
pronouns: "she" | "her"
located_in: Mumbai, India
title: "Research Assistant - FOSSEE , IIT Bombay | VLSI & IC Design Enthusiast"
skills:
- RTL Design: [Verilog HDL, Digital Design, Simulation & Verification]
- Analog & Mixed-Signal Basics
- EDA Tools: [eSim, Ngspice, KiCad, Vivado, Quartus Prime, Multisim, Proteus]
- Programming: [C]
education:
- "Bachelor's in Electronics and Communication Engineering"
- "IIIT Nuzvid (Rajiv Gandhi University of Knowledge and Technologies)"
- 2021-2025
technical_experience:
- "Research Assistant - FOSSEE eSim, IIT Bombay"
- "Contributor - Open Source EDA Tool Development (eSim)"
- "Semester long Intern IIT Bombay - Digital IC Design
projects:
- "Digital SerDes (Serializer/Deserializer) using Verilog"
- "DCTQ Processor for Image Compression (JPEG/MPEG)"
- "FPGA-Based Line Follower Robot (DE10 Nano)"
- "Mobile Controlled Robot using UART (FPGA)"
- "eSim IC Component Design & Validation (8+ ICs)"
- "Hover Board (IOT Application)"
fields_of_interest:
- "VLSI Design"
- "Digital IC Design"
- "Analog & Mixed-Signal IC Design"
- "Semiconductor Design & EDA Tools"
certifications:
- NPTEL: Digital Electronics
PCB Design
RTL to GDS Flow
Industrial IoT
- Crash Course on C# from Lernx
achievements and publications:
- "Inspire Award Winner (District & State Level)"
- "FPGA Innovation Contest Recognition"
- "An Offline AI Assistant for eSim: Easier, Accessible, Open-Source Circuit Design and Debugging-opportunity Open Source Conference 3.0, OOSC IIT Kanpur ·"
- "From Containers to Chip Design Classrooms: Leveraging Snap and Docker to Enable Open-Source EDA with eSim - Opportunity Open Source Conference 3.0, OOSC IIT Kanpur ·"
current_focus:
- "Open-source EDA Development (eSim)"
- "RTL Optimization & Digital IC Design"
contact:
- LinkedIn: "linkedin.com/in/shanthi-priya20"
- Gmail: "kshanthipriya20@gmail.com"