Fix LARS/LAMB optimizer support and non-contiguous tensor handling on XPU#1902
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jiqing-feng wants to merge 3 commits intobitsandbytes-foundation:mainfrom
Open
Fix LARS/LAMB optimizer support and non-contiguous tensor handling on XPU#1902jiqing-feng wants to merge 3 commits intobitsandbytes-foundation:mainfrom
jiqing-feng wants to merge 3 commits intobitsandbytes-foundation:mainfrom
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Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
Signed-off-by: jiqing-feng <jiqing.feng@intel.com>
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Changes
Enable LARS/LAMB optimizers on XPU: Added missing
"lars"and"lamb"entries toname2optimizer_id,name2optimizer_32bit_fn, andname2optimizer_fndicts in the Triton backend, andname2optimizer_idin the default backend. LARS maps toMOMENTUM(1-state) and LAMB maps toADAM(2-state).Fix Triton compilation error with fp16 gradients: In
_optimizer_precondition_1state_32bit, the MOMENTUM branch'sstep == 1path doess1_vals = g_vals(direct assignment). When gradients are fp16, this changess1_valsfrom fp32 to fp16, conflicting with theelsebranch where arithmetic auto-promotes to fp32. Fixed by castingg_valsto fp32 at the assignment site.Fix non-contiguous tensor support for blockwise quantization: Triton kernels use linear offsets to access memory, which is incorrect for non-contiguous tensors. Added
.contiguous()calls inquantize_blockwiseanddequantize_blockwiseentry points.Related tests:
Hi @matthewdouglas . Would you please review this PR? Thanks!