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1. mjpegZero mjpegZero Public

   Open source synthesizable MJPEG encoder written in behavioral Verilog 2001 with AXI interfaces, up to 1080p30 on low end AMD/Xilinx 7-Series FPGAs. Two operating modes: Full encodes with runtime qu…

   Verilog 1

2. axiZero axiZero Public

   Open source AXI4 / AXI4-Lite interconnect generator. Describe your bus topology in YAML, get you Verilog back

   Verilog 1

3. fpgaZeroMCP fpgaZeroMCP Public

   An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.

   Python 1

4. fresca fresca Public

   Versatile multi-sensor temperature controller

   C++ 11 2

5. crcZero crcZero Public

   Forked from bard0-design/crcZero

   Generates synthesizable VHDL & Verilog, parallel CRC modules from a built-in catalog of 80+ named algorithms, or from user-supplied polynomial parameters. Optional AXI4-S wrappers, Self-checking te…

   Python