CLI tools to extract and display port definitions from Verilog files and generate repository file-trees to make navigation and interaction with my hardware projects easier for anyone. Automatically fetched as utils package along any of my repository downloads through download_repos.bat/.sh scripts that are hosted on each repo 😄.
cli parser eda rtl hdl verilog-hdl filetree cli-tool verilog-parser utils-tools markdown-output port-extraction default-box-output repo-filetree-generator
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Updated
Mar 21, 2026 - Lua